新的OLED像素电路及其抑制电压漂移的a-Si：H TFT的驱动方法_ESSAY

新的OLED像素电路及其抑制电压漂移的a-Si：H TFT的驱动方法-留学生论文46.2: New OLED Pixel Circuit and Driving Method to Suppress Threshold Voltage Shift of a-Si:H TFT

Taro Hasumi, Shinji Takasugi, Keigo Kanoh, Yoshinao Kobayashi

R&D Center, Kyocera Display Institute Co., Ltd., Yamato-Shi, Kanagawa, Japan

摘要 Abstract

提出一种新的有机发光二极管（OLED）的像素以此来补偿电路，可变电容器阈值电压（Vth）完全转移，同时也提出了一个像素驱动的方法来抑制Vth偏移。We propose a new organic light-emitting diode (OLED) pixel circuit with a variable capacitor that allows to compensate threshold voltage (Vth) shift completely, and also propose a pixel driving method to suppress Vth shift. http://www.ukassignment.org/dxessay/

简介 1. Introduction

Amorphous silicon (a-Si) TFT arrays are widely used in the LCD industry and they are one of the most cost-effective candidates for active-matrix organic light-emitting diode displays (AMOLEDs) [1] [2]. However, a-Si TFTs have been considered to have a severe Vth shift caused by long-time operations, which results in luminance deterioration and image sticking of display devices. 目标是抑制Vth偏移，并补偿Vth偏移，并且使用的a-Si TFT作为AMOLED显示器的可靠底板。Our objective is to suppress Vth shift and to compensate Vth shift completely if any, and to use a-Si TFTs as a reliable backplane for AMOLEDs.

放电模式的a-Si：H TFT驱动 2. Discharging Mode for a-Si:H TFT Driving

Vth shift of a-Si TFTs due to consecutive gate biases has been regarded as the most difficult issue for the use of a-Si TFTs as an AMOLED backplane. Two possible mechanisms of the instability of a-Si TFTs have been investigated; one is creation of metastable states on a-Si:H and the other is charge trapping in the silicon nitride gate insulator [3]. Although it is not clear yet which of the two mechanisms dominates the instability, some experimental results indicate that applying a negative bias suppresses Vth shift, which occurs during positive bias periods [4]. We investigated negative bias conditions in detail on bias and time dependencies of suppression of Vth shift.
We measured Vth shift of driving TFTs with the following “Constant Current BTS” method: a driving TFT is controlled to have a constant drain current (Ids) by automatically adjusting its gate bias (Vgs), while its drain bias (Vds) is fixed to a constant voltage. Assuming that mobility degradation is negligible, we treat gate bias shift (Vgs - Vth) is equal to Vth shift. Under our testing condition (mobility = 0.5cm/Vs2, Cox = 17nF/cm2, Ids = 0.4μA, Vds = 6V), mobility degradation did not occur. We can therefore regard V0 (Vgs - Vth) shift as the Vth shift of the driving TFT. A gate bias was automatically applied for the TFT to have an Ids of 0.4μA (V0 is a positive value around 3V). We also raised the environment temperature to 40°C, emulating OLED heat. At certain predetermined intervals, which we call discharging mode, the gate bias was set to negative.

Some of our results are shown in Figs. 1-3 (points are actual drifts of V0, and lines are approximation lines), in which tests we applied negative biases -1V or -5V for 20min, after applying a positive bias for 10min. It is clear from the slopes of V0 shift that negative biases suppress Vth shift. The TFT of a bias of -5V has a Vth shift of nearly 0, which indicates we can suppress Vth shift of a-Si TFTs significantly by selecting an appropriate negative bias.

No Discharing

0.01

0.1

0.01 1 100 10000

Stressed time[H]

ΔＶ0

after 10000h

Vth shift = 2.7V

Figure 1:Vth Shift of BTS Test without Discharging

Discharging -1V

0.01

0.1

0.01 1 100 10000

Stressed time[H]

ΔＶ0

after 10000h

Vth shift = 1.2V

Figure 2:Vth shift of BTS Test with –1V discharging

Discharging -5V

0.01

0.1

0.01 1 100 10000

Stressed time[H]

ΔＶ

after 10000h

Vth shift = 0.08V

Figure 3 Vth shift of BTS Test with –5V discharging We have also checked shorter periods and found out even 15s and 60s of a negative bias (Vgs = -5V, Vds = 0V) also suppressed Vth shift significantly. Figs. 4 and 5 are the BTS results of 15s and 60s of a negative bias of -5V. The stress condition was the same as that of Figs. 1-3. The result of -5V for 15s is better than that of Fig. 1, and we see from these results that we can easily use

46.2 / T. Hasumi

discharging mode to suppress Vth shift for actual display

applications such as when a display is turned off for battery

saving.

Discharging -5V for 15seconds.

0.01

0.1

0.01 1 100 10000

Stressed time[H]

ΔＶ0

after 10000h

Vth shift = 0.51V

Figure 4 Vth shift of BTS Test with –5V 15s discharging

Discharging -5V for 60seconds.

0.01

0.1

0.01 1 100 10000

Stressed time[H]

ΔＶ0

after 10000h

Vth shift = 0.34V

Figure 5 Vth shift of BTS Test with –5V 60s discharging Our design assumption for AMOLED TFTs is that the maximum Ids for a driving TFT is 0.1μA through 5μA, and we use driving TFTs only in their saturation region even at the maximum pixel luminance. We calculated that the gate bias (Vgs - Vth) of driving TFTs will be lower than 5V. At these stress conditions,Vth shift of stressed TFTs recovers at 230°C annealing, while mobility degradation does not occur.

0.E+00

2.E-05

4.E-05

6.E-05

8.E-05

1.E-04

0 5 10 15 20

Vgs[V]

Ids[A]

Before Stress

After Stress

Stress+Anneal

Vth Shift

by Stress

Recover by

Anneal

Figure 6 Before Stress/After Stress/Stress+Anneal IV Curve Fig. 6 shows the initial, stressed (caused a Vth shift of 8V), and after-annealing Id-Vg curves. We can see that the TFT recovered from Vth shift completely, which result suggests Vth shift of a-Si TFTs is due to a metastable change of a-Si:H, and the change can be cured through negative biases or annealing.

3. Complete Vth Compensation

新型TFT像素电路 3.1 Novel 2-TFT Pixel Circuit

Fig. 7 shows our novel 2-TFT pixel circuit of complete Vth compensation.

COLED

VSS line

Data line

CgsTth OLED

CgsTd

CgdTd

Scan line

CgdTth

VDD line

Cvar Tth

Figure 7 Novel 2-TFT pixel circuit

每个像素电路的驱动用TFT（Td）的一个Vth的检测TFT（Tth），存储电容（Cs），可变电容器（CVAR），和一个OLED，并连接到对应的扫描线及数据线VDD线的和VSS线。Each pixel circuit has a driving TFT (Td), a Vth sense TFT (Tth), a storage capacitor (Cs), a variable capacitor (Cvar), and an OLED, and is connected to corresponding scan line and data line,and to the common VDD line and VSS line. The OLED capacitance (COLED) and unintentional parasitic capacitances of TFTs (CgdTd, CgsTd, CgdTth, CgsTth) are also shown. We have found that because of the parasitic capacitances, we usually cannot compensate Vth just by Vth sense. We introduce the variable capacitor to compensate Vth completely.

3.2 Driving Scheme

Fig. 8 shows the driving waveforms of the 2-TFT pixel circuits.

VDD line

VSS line

Preparation

Vth sense

Writing Emission

-Vp

VDD

Scan line 1 VgH

VgL

Data line VdH

Reset Cs Reset OLED

-Vp

VgH

VgL Scan line 2

scan

Figure 8 Pixel driving waveforms

Pixel rows are scanned vertically during the writing period, while other periods including the emission period are simultaneous.

46.2 / T. Hasumi

When the Vth sense period ends, Cs and COLED of each pixel hold a voltage of Vth + a, where Vth is the threshold voltage of the Td of the pixel and a is a constant depending on the duration of the Vth sense period and the capacitance ratio of the pixel.

3.3 Voltage Calculation

Before calculating a pixel voltage, we define the following two capacitances:

Call = COLED + Cs + CgsTthon + CgdTthon + CgsTdoff + Cvaron#p#分页标题#e#

Call’ = Cs + CgsTthoff + CgsTdon + CgdTdoff + Cvaroff

The parasitic capacitances have different capacitance values when the corresponding TFT is on and off, and we use suffixes to distinguish them here. Likewise, the variable capacitor has two capacitance values. We also define three capacitance differences

here:

ΔCgsTd = CgsTdon - CgsTdoff

ΔCgsTth = CgsTthon - CgsTthoff

ΔCvar = Cvaron - Cvaroff

When the image data voltage Vdata is written to a pixel, the Td gate voltage Vgswrite is calculated as follows: Vgswrite = Vth + a + (Cs / Call) Vdata

The Td gate voltage Vgs during the emission period is calculatedas follows:

Vgs = {(Cs + CgsTthon + CgsTdoff + Cvaron) / Call’} (Vth + a) +

{Cs (COLED + CgdTthon) / (Call Call’)} Vdata + {-(CgsTthon +

Cvaron) VgH + (CgsTthoff + Cvaroff) VgL + CgdTdoff Vds} / Call’

The value of ∂(Vgs - Vth)/∂Vth must be 0 in order to compensate

Vth completely.

∂(Vgs - Vth)/∂Vth = (-CgsTdon - ΔCgsTd + ΔCgsTth + ΔCvar) =

∴ ΔCvar = CgsTdon + ΔCgsTd - ΔCgsTth

In this case Vgs can be simplified to:

Vgs = Vth + b Vdata + c

where b and c are constant. Since Ids is given in the following equation, we obtain the same Ids for the same Vdata:

Ids = (β / 2) (Vgs - Vth)2 = (β / 2) (b Vdata + c)2

Since Td is larger than Tth, (CgsTdon + ΔCgsTd) is larger than ΔCgsTth. We need a variable capacitor large enough to compensate Vth.

3.4 Slit MIS Capacitor

为了在有限的空间中形成的可变电容器像素，我们引入一个金属 - 绝缘体 - 半导体（MIS）电容，一个新的可变电容器组成的平常源极/漏极层和a-Si层。 In order to form a variable capacitor in the limited space of a pixel, we introduce a slit metal-insulator-semiconductor (MIS) capacitor, a novel variable capacitor consisting of usual gate and source/drain layers and an a-Si layer. Fig. 10 shows the concept of the slit MIS capacitor. M1 is the gate layer and M2 is the source/drain layer, although a slit capacitor does not function as a transistor. When the M1 voltage is low, a-Si becomes an insulator and the M1/M2 overlapping area works as a capacitor.

When the M1 voltage is high, a-Si becomes a conductor and the M1/a-Si overlapping area works as a capacitor. We put a slit MIS capacitor in a pixel to compensate the parasitic capacitances,and we can completely compensate Vth shift if any.

a-Si

Figure 10 The concept of the slit MIS capacitor

Fig. 11 shows actual data of capacitance per area of a plain metalinsulator-metal (MIM) capacitor, a plain MIS capacitor, and a slit MIS capacitor of a line width of 3μm and a slit width of 6μm.

Fig. 12 shows the relationship of the slit width and capacitance per area when the line width is fixed to 3μm.

100

120

140

160

180

200

-20 -15 -10 -5 0 5 10 15 20

Bias [V]

Capacitance per area [μF/m2]

M1/M2

M1/a-Si/M2

M1/a-Si/M2 slit3/6

Figure 11 Bias vs. capacitance per area

100

150

200

0 10 20 30 40

Slit width (μm)

Capacitance per area (μF/m2)

Bias = -20V

Bias = +20V

Figure 12 Slit width vs. capacitance per area

3.5 Effect of Complete Vth Compensation

By properly designing the size of the variable capacitor, we have successfully compensated Vth completely. Actual luminance

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data with and without complete Vth compensation tests are shown

in Figs. 13 and 14.

0 32 64 96 128 160 192 224 256

Level

Luminance1/2 (cd1/2/m)

100h

300h

500h

Figure 13 Luminance (Complete Vth Compensation)

0 32 64 96 128 160 192 224 256

Level

Luminance1/2 (cd1/2/m)

100h

300h

500h

Figure 14 Luminance (Incomplete Vth Compensation)

4. Fabrication of a-Si:H Driven AMOLEDs

Using the above-mentioned 2-TFT pixel with complete Vth compensation, we have successfully fabricated 2.4” qVGA a-Si:H driven AMOLEDs.

The specification of the AMOLEDs is described in Table 1, and a photograph of one of them is shown in Fig. 15.

Size 2.4"

Format qVGA (320 x 240)

Resolution 166ppi

Contrast Ratio 2000:1>

Peek Brightness 200cd/m2

Color Saturation (NTSC) 90%

Table 1 The specification of the actual AMOLED

Figure 15 A photograph of one of our AMOLEDs

结论 5. Conclusion

结合的放电模式和完整的Vth补充我们已经成功地抑制了的a-Si TFT的阈值电压偏移，这样我们从而提出a-Si TFT可以作为一个在技术上和经济上可行的AMOLED背板。Combining the discharging mode and complete Vth compensation we have successfully suppressed Vth shift of a-Si TFTs, and we thus propose a-Si TFTs as a technologically and economically viable AMOLED backplane.

6. Acknowledgements

We would like to thank Kazuo Inamori and Yasuo Nishiguchi for supporting this research and development operation. We also thank Hidenori Miyata and Mototsugu Ohhata for their leadership.

We give thanks to all the colleagues in Kyocera Display Institute for effective suggestions and cooperation.

7. References

[1] T. Tsujimura et al., “A 20-inch OLED Display Driven by

Super-Amorphous-Silicon Technology”,

SID 03 Digest, pp6-9, 2003.

[2] S. Ono et al., “Pixel Circuit for a-Si AM-OLED”,

IDW '03 Digest, pp255-258, 2003.

[3] M. J. Powell, “Bias-stress-induced creation and removal of

dangling-bond states in amorphous silicon thin-film

transistors”, Appl. Phys. Lett. Vol 60, pp207-209, 1992.

[4] J. H. Lee et al., “A New a-Si:H TFT Pixel Circuit

Suppressing OLED Current Error Caused by the Hysteresis

and Threshold Voltage Shift for Active Matrix Organic Light

Emitting Diode”, SID 05 Digest, pp228-231, 2005.