A New Digital Interface需要一个新的数字接口的原因

Why Displays Require A New Digital Interface显示器需要一个新的数字接口的原因

This paper provides a technical overview ofDisplayPort Ver.1.0, a truly open, pending VESA

本文提供的一个真正开放的，VISA系统的Port1.0版的技术方面的概述。 http://www.ukassignment.org/uklunwen/

Abstract:摘要

 This paper provides a technical overview ofDisplayPort Ver.1.0, a truly open, pending VESA standardfor A/V connectivity.本文提供的Display是Port1.0版，一个真正开放的，VESA标准的A / V连接性的技术方面的概述。 DisplayPort is designed to be ascalable and extensible technology foundation for sendingdigital display and associated data not only between a PCand a display but also between ICs within a system. Itsmaximum bandwidth is sufficient to support 2560x1600-resolution with pixel bit depth of 30 bits per pixel over asingle DisplayPort cable.

 For inside-the-box application, itreduces the number of wires:对于内箱所应用程序，它可以减少导线的数量： LCD panel resolution of up to1680x1050 can be supported over a single high-speeddifferential pair. DisplayPort consists of a uni-directionalMain Link for transporting isochronous A/V streams fromSource device to Sink device and a half-duplex, bi-directional AUX CH used for realizing robust plug-n-playease of use. Both Main Link and AUX CH are made of AC-coupled differential pairs. The Main Link may have 1, 2, or4 pairs (or lanes), each capable of supporting applicationbandwidth of 270Mbytes/second while AUX CH has 1 pair.DisplayPort requires no pair for forwarding clock, thusenabling the maximum usage of the differential pairs.Adopting a layered and modular architecture, DisplayPortcan take leverage the advancement of the Physical Layerwithout affecting upper layers. Based on “micro-packet”architecture, DisplayPort is seamlessly extensible forsupporting transport of multiple A/V streams and otherdata types for new display applications.基于“微封包架构之上，显示的是无缝扩展技术，这项技术是在多个A/ V的流和其他数据类型来作为新的显示应用。

Structure of DisplayPort显示端口的结构

The DisplayPort link consists of the Main Link, AUX CH,and the Hot Plug Detect (HPD) signal line. 显示端口的链路由主链路，辅助通道和热插拔检测（HPD）信号线。组成As shown in thefollowing diagram, the Main Link is a uni-directional, high-bandwidth, and low-latency channel used for transport ofisochronous streams such as uncompressed video and audio.AUX CH is a half-duplex, bi-directional channel used forlink management and device control. The HPD signal alsoserves as an interrupt request by the Sink device.

Main Link主要链路

The Main Link consists of AC-coupled, doubly-terminateddifferential pairs, or lanes. 主链路由交流耦合，双端差分对，或车道构成。AC-coupling allows theDisplayPort transmitter and receiver to have differentcommon mode voltages. This facilitates the silicon processmigration into deep sub-micron (for example, 65 nmCMOS process) while supporting the 0.35 um CMOSprocess still common for LCD panel TCON (timingcontroller) chips.

Two link rates are supported: 2.7Gbps and 1.62Gbps perlane. 两个链路支持的2.7Gbps的和1.62 GBŞ的速率。The link rate is decoupled from the pixel rate. Thepixel rate is regenerated from the link symbol clock usingthe time stamp values M and N. The capabilities of theDisplayPort transmitter and receiver, and the quality of thechannel (that is, a cable) will determine whether the linkrate is set to 2.7Gbps or 1.62Gbps per lane.

The number of lanes of the Main Link is 1, 2, or 4 lanes.主连接的线的数量是1，2或4条车道数。The number of lanes is decoupled from the pixel bit depth(bits per pixel, or bpp) and component bit depth (bits percomponent, or bpc). Component bit depths of 6, 8, 10, 12,and 16 are supported with the colorimetry formats of RGB,YCbCr444/422 in DisplayPort proposed Version 1.0,regardless of the number of Main Link lanes.

All lanes carry data: there is no dedicated channel forforwarding clock. The link clock is extracted from the datastream itself that is encoded with ANSI8B/10B coding rule(specified in ANSI X3.230-1994, clause 11).

Source and Sink devices are allowed to support theminimum number of lanes required for their needs. 源和接收器设备是允许在支持最小时间为他们的提供所需的车道。Thedevices that support 2 lanes are required to support both 1and 2 lanes, while those that support 4 lanes are required tosupport 1, 2, and 4 lanes. The external cable that isdetachable by an end user is required to support 4 lanes formaximizing the interoperability between Source and Sinkdevices. When fewer than 4 lanes are enabled, those laneswith lower lane numbers (from Lane 0) must be used.

Excluding the 20% channel coding overhead, theDisplayPort Main Link provides for the applicationbandwidth (also called link symbol rate) of 270Mbytes persecond per lane at a high bit rate mode and 162Mbytes persecond per lane at a low bit rate mode.DisplayPort devices may freely trade pixel bit depths withthe resolution and frame rate of a stream within theavailable bandwidth. Examples are shown below.